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| SERIAL PRESENCE DETECT PC100 Registered DIMM PC100 Registered DIMM(168pin) Intel Type Rev1.2 SPD Specification(256Mb B-die base) Rev. 0.0 January 2000 Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT M377S3253BT3-C1H/C1L (1.2 ver ) *Organization : 32MX72 *Composition : 32MX8 * 9ea *Used component part # : K4S560832B-TC1H/1L *# of banks in module : 1 Row *# of banks in component : 4 banks *Feature : 1,500 mil height & double sided component *Refresh : 8K/64ms *Contents : Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns ECC PC100 Registered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 13 10 1 Row 72 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Dh 0Ah 01h 48h 00h 01h A0h 60h 02h 82h 08h 08h 01h 8Fh 04h 06h 01h 01h 1Fh Note 1 1 2 2 7.8us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2& 3 0 CLK 0 CLK Registered/Buffered DQM, address & control inputs and On-card PLL +/- 10% voltage tolerance, 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 40h 20h 10h 20h 2 2 2 2 1 Row of 256MB 2ns 1ns 2ns Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Samsung memory) Manufacturer part # (Samsung memory) Manufacturer part # (Memory module) Manufacturer part # (Memory type & edge connector) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module density) ...... Manufacturer part # (Module density) Manufacturer part # (Refresh, # of banks in Comp. & interManufacturer part # (Compositon component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) Module Supports this CLK Frequency Attributes for CLK frequency defined Unused storage locations 1 H Blank 3 B-die (3rd Gen.) Undefined 100MHz PC100 Registered DIMM Function Supported -1H 1ns Current release Intel spd 1.2A Samsung Samsung Onyang Korea M 3 Blank 7 7 S 3 2 5 3 B T 3 "-" C 1 L 31h 48h 20h 33h 42h 64h 8Fh 8Dh 5 3 3 4 5 6Ah CEh 00h 01h 4Dh 33h 20h 37h 37h 53h 33h 32h 35h 33h 42h 54h 33h 2Dh 43h 31h 4Ch -1L -1H 10h 00h 12h 9Ah Hex value -1L Note Detailed 100MHz Information Undefined Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung' own Assembly Serial # system. All modules may have different unique serial #. s 5. These bytes are Undefined and can be used for Samsung' own purpose. s Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT M377S6450BT3-C1H/C1L (1.2ver) * Organization : 64MX72 * Composition : 64MX4 *18 * Used component part # : K4S560432B-TC1H/C1L * # of rows in module : 1 Row * # of banks in component : 4 banks * Feature : 1,700 mil height & double sided component * Refresh : 8K/64ms * Contents : Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns ECC PC100 Registered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 13 11 1 Row 72 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Dh 0Bh 01h 48h 00h 01h A0h 60h 02h 82h 04h 04h 01h 8Fh 04h 06h 01h 01h 1Fh Note 1 1 2 2 7.8us, support self refresh x4 x4 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Registered/Buffered DQM, address & control inputs and On-card PLL +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 80h 20h 10h 20h 2 2 2 2 1 Row of 512MB 2ns 1ns 2ns Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interManufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz Intel Specification details Unused storage locations 1 H Blank 3 B-die(3rd Gen.) Undefined 100MHz PC100 Registered DIMM Function Supported -1H 1ns Current release Intel spd 1.2A Samsung Samsung Onyang Korea M 3 Blank 7 7 S 6 4 5 0 B T 3 "-" C 1 L 31h 48h 20h 33h 42h 64h 8Fh 8Dh 5 3 3 4 5 A3h CEh 00h 01h 4Dh 33h 20h 37h 37h 53h 36h 34h 35h 30h 42h 54h 33h 2Dh 43h 31h 4Ch -1L -1H 10h 00h 12h D3h Hex value -1L Note Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT M377S6453BT0-C1H/C1L (1.2ver) * Organization : 64MX72 * Composition : 32MX8 *18 * Used component part # : K4S560832B-TC1H/C1L * # of rows in module : 2 Rows * # of banks in component : 4 banks * Feature : 1,700 mil height & double sided component * Refresh : 8K/64ms * Contents : Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns ECC PC100 Registered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 13 10 2 Rows 72 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Dh 0Ah 02h 48h 00h 01h A0h 60h 02h 82h 08h 08h 01h 8Fh 04h 06h 01h 01h 1Fh Note 1 1 2 2 7.8us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Registered/Buffered DQM, address & control inputs and On-card PLL +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 40h 20h 10h 20h 2 2 2 2 2 Rows of 256MB 2ns 1ns 2ns Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interManufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz Intel Specification details Unused storage locations 1 H Blank 0 B-die(3rd Gen.) Undefined 100MHz PC100 Registered DIMM Function Supported -1H 1ns Current release Intel spd 1.2A Samsung Samsung Onyang Korea M 3 Blank 7 7 S 6 4 5 3 B T 0 "-" C 1 L 31h 48h 20h 30h 42h 64h 8Fh 8Dh 5 3 3 4 5 6Bh CEh 00h 01h 4Dh 33h 20h 37h 37h 53h 36h 34h 35h 33h 42h 54h 30h 2Dh 43h 31h 4Ch -1L -1H 10h 00h 12h 9Bh Hex value -1L Note Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT M377S2858BT3-C1H/C1L (1.2ver) * Organization : 128MX72 * Composition : 128MX4 *18 * Used component part # : K4S510632B-TC1H/C1L * # of rows in module : 2 Rows * # of banks in component : 4 banks * Feature : 1,700 mil height & double sided component * Refresh : 8K/64ms * Contents : Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns ECC PC100 Registered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 13 11 2 Rows 72 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Dh 0Bh 02h 48h 00h 01h A0h 60h 02h 82h 04h 04h 01h 8Fh 04h 06h 01h 01h 1Fh Note 1 1 2 2 7.8us, support self refresh x4 x4 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Registered/Buffered DQM, address & control inputs and On-card PLL +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 80h 20h 10h 20h 2 2 2 2 2 Rows of 512MB 2ns 1ns 2ns Rev. 0.0 Jan. 2000 SERIAL PRESENCE DETECT SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interManufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz Intel Specification details Unused storage locations 1 H Blank 3 B-die(3rd Gen.) Undefined 100MHz PC100 Registered DIMM Function Supported -1H 1ns Current release Intel spd 1.2A Samsung Samsung Onyang Korea M 3 Blank 7 7 S 2 8 5 8 B T 3 "-" C 1 L 31h 48h 20h 33h 42h 64h 8Fh 8Dh 5 3 3 4 5 A4h CEh 00h 01h 4Dh 33h 20h 37h 37h 53h 32h 38h 35h 38h 42h 54h 33h 2Dh 43h 31h 4Ch -1L -1H 10h 00h 12h D4h Hex value -1L Note Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev. 0.0 Jan. 2000 |
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